1. Field of the Invention
The present invention relates to a semiconductor device comprising a heterojunction type MIS transistor and, more particularly, to such a semiconductor device which can operates at a reduced voltage with its operation speed kept high.
2. Description of the Related Art
In recent years, battery-operated personal digital assistant apparatus has been widely used. It is strongly desired that such an apparatus operate at a reduced power supply voltage while keeping high-speed operation performance in order to extend the life of the battery used.
The power consumption (Pload) of a circuit comprising a complementary MIS device (cMIS device), which is caused predominantly by charge-discharge of load, is represented by the following expression (1):Pload=f·Cload·VDD2  (1)wherein f is an operation frequency of load, Cload is a load capacitance and VDD is a power supply voltage. As can be understood from the formula (1), reducing the power supply voltage VDD is very effective in reducing the power consumption. However, the operation speed of MIS transistors, in general, also lowers with lowering power supply voltage. It is therefore desired that the power supply voltage of a MIS transistor be reduced and, at the same time, the high-speed operation performance of the MIS transistor be maintained as it is.
Although lowering of the threshold voltage of a MIS transistor is effective in realizing a high-speed operation (i.e., a high driving power) with a high on-current being ensured at a low power supply voltage, generally the subthreshold leakage current increases exponentially with lowering threshold voltage. In a circuit comprising a cMIS device, power consumption based on charge-discharge of load does not occur in a stand-by state and, hence, the proportion of power consumption based on the subthreshold leakage current to the power consumption of the chip increases. As the art of reducing such a subthreshold leakage current in the stand-by state, there is known a VTMIS device (Variable Threshold-Voltage MIS device) of which the threshold voltage is controlled by varying the substrate bias, as taught by literature document 1 (T. Kuroda et. Al., “A 0.9V, 150-MHz, 10-mW, 4 mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme,” IEEE J. Solid-State Circuits, vol.31, 1996, p.1770.), for example. When the VTMIS device is in its operating state, a high-speed operation is ensured in the device by applying a reduced substrate bias to lower the threshold voltage of the MIS transistor, whereas when the device is in its stand-by state, the leakage current is reduced in the device by applying an enhanced substrate bias to raise the threshold voltage of the MIS transistor. A MOS transistor, which is capable of controlling its threshold voltage by varying the substrate bias like the aforementioned VTMIS device, is described in literature document 2 (Japanese Patent Laid-Open Gazette No. 2000-260991, paragraphs [0004] to [0007]).
Such a VTMIS device, however, involves the following problem.
In order for a MIS transistor to realize a high-speed operation in its operating state as well as a low leakage current in its stand-by state, the threshold voltage of the MIS transistor has to shift largely with varying substrate bias. As the power supply voltage will be lowered increasingly from now on, it will be difficult to obtain a large shift in the threshold voltage of the MIS transistor. A change in threshold voltage (ΔVth) due to a change in substrate bias (ΔVbs) is represented by the following expression (2):ΔVth=γ·ΔVbs  (2)wherein γ is a substrate bias coefficient.
Since a reduction in threshold voltage Vth and an improvement in substrate bias coefficient γ are in a tradeoff relation to each other as taught by literature document 3 (T. Hiramoto et. Al., “Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias,” IEICE Trans. Electron., vol.E83-C, 2000, p.161), a MIS transistor having a low threshold voltage has decreased substrate bias coefficient γ undesirably. Therefore, if the threshold voltage Vth of the MIS transistor in the operating state is lowered to lower the power supply voltage of the transistor as well as to realize a high-speed operation (i.e., a high driving power), the substrate bias coefficient γ decreases accordingly and, hence, the amount of change ΔVth in threshold voltage Vth decreases, as can be understood from the expression (2). That is, even if the MIS transistor is applied with a strong substrate bias in the stand-by state, the amount of change Δ Vth from the threshold voltage Vth of the transistor in the operating state to that of the transistor in the stand-by state is not made large enough. As a result, it might be difficult to suppress the subthreshold leakage current of the MIS transistor sufficiently.
It should be noted that literature document 4 (Japanese Patent Laid-Open Gazette No. 2001-210831) discloses a MIS transistor having a low threshold voltage and a wide operating voltage range.